Axi4 interface definition
Definition of the Write/Read address channel
Definition of the Write response channel
Definition of the Write response channel
Axi4 configuration class
Configuration class for the Axi4 bus
Definition of the Read Data channel
Definition of the Read Data channel
Axi4 configuration class
Converts Axi4 burst streams into single beat transactions and adds last as required.
Converts Axi4 burst streams into single beat transactions and adds last as required. AR channel will block if the pending transactions FIFO is full for that ID.
Warning, the implementation currently work only for in order ar -> r responses
Axi4 <-> BRAM bus with burst WARNING do not support byte mask !!
Definition of the Write data channel
Definition of the Write data channel
Axi4 configuration class
Created by spinalvm on 13.06.17.
Converts Axi4 burst streams into single beat transactions and generates a single write response.
Converts Axi4 burst streams into single beat transactions and generates a single write response. AW channel will block if the pending transactions FIFO is full for that ID.
Definition of the constants used by the Axi4 bus
State of the state machine of the wrapper
Axi4 interface definition
Axi4 configuration class