AxiMemorySimConfig

new AxiMemorySimConfig(maxOutstandingReads: Int = 8, maxOutstandingWrites: Int = 8, readResponseDelay: Int = 0, writeResponseDelay: Int = 0, interruptProbability: Int = 0, interruptMaxDelay: Int = 0, defaultBurstType: Int = 1, useAlteraBehavior: Boolean = false)

useAlteraBehavior
Couple write command and write channel as in the Altera Cyclone 5 F2H_SDRAM port.

final def !=(arg0: Any): Boolean

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final def ##(): Int

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final def ==(arg0: Any): Boolean

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final def asInstanceOf[T0]: T0

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def clone(): AnyRef

Attributes
protected[java.lang]
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Annotations
@HotSpotIntrinsicCandidate() @throws( ... )
val defaultBurstType: Int
final def eq(arg0: AnyRef): Boolean

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final def getClass(): Class[_]

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Annotations
@HotSpotIntrinsicCandidate()
val interruptMaxDelay: Int
val interruptProbability: Int
final def isInstanceOf[T0]: Boolean

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Any
val maxOutstandingReads: Int
val maxOutstandingWrites: Int
final def ne(arg0: AnyRef): Boolean

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final def notify(): Unit

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Annotations
@HotSpotIntrinsicCandidate()
final def notifyAll(): Unit

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Annotations
@HotSpotIntrinsicCandidate()
val readResponseDelay: Int
final def synchronized[T0](arg0: ⇒ T0): T0

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val useAlteraBehavior: Boolean

Couple write command and write channel as in the Altera Cyclone 5 F2H_SDRAM port.
final def wait(arg0: Long, arg1: Int): Unit

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Annotations
@throws( ... )
final def wait(arg0: Long): Unit

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@throws( ... )
final def wait(): Unit

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Annotations
@throws( ... )
val writeResponseDelay: Int